DMAC
9
9.3 Functional Description of the DMAC
9.3.3 Starting DMA
Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Channel
Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or source of
DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1". DMA transfer begins when
the specified cause or source of DMA transfer request becomes effective after setting the TENL (DMA transfer
enable) bit to "1".
Note: • If the transfer request source selected by the REQSL (DMA transfer request source select) and
REQESEL (extended DMA transfer request source select) bits is MJT (TIN input signal), the time
required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN input
signal is three cycles (150 ns when the internal peripheral clock = 20 MHz) at the shortest. Or,
depending on the preceding or following bus usage condition, up to five cycles (250 ns when the
internal peripheral clock = 20 MHz) may be required. (However, this applies when the external
bus, HOLD and the LOCK instruction all are unused.)
To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input
signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Section 21.7, “AC
Characteristics (when VCCE = 5 V),” and Section 21.8, “AC Characteristics (when VCCE = 3.3 V).”)
9.3.4 DMA Channel Priority
DMA0 has the highest priority. The priority of this and other channels is shown below.
DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9
This order of priority is fixed and cannot be changed. Among channels on which DMA transfer is requested, the
channel that has the highest priority is selected.
9.3.5 Gaining and Releasing Control of the Internal Bus
For any channel, control of the internal bus is gained and released in “single transfer DMA” mode. In single
transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA transfer
request is accepted and after executing one DMA transfer (in one read and one write internal clock cycle),
returns bus control to the CPU. The diagram below shows the operation in single transfer DMA.
Requested
Gained
Requested
Gained
Requested
Gained
Internal bus arbitration
(requests from the DMAC)
CPU
Released
Released
Released
Internal bus
R
W
R
W
R
W
DMAC
One DMA transfer
One DMA transfer
One DMA transfer
R: Read
W: Write
Figure 9.3.2 Gaining and Releasing Control of the Internal Bus
32180 Group User’s Manual (Rev.1.0)
9-34
RENESAS [ RENESAS TECHNOLOGY CORP ]
