DMAC
9.3 Functional Description of the DMAC
9
9.3.2 DMA Transfer Processing Procedure
Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0.
DMA transfer
processing starts
Setting interrupt
controller-related
registers
Set the interrupt controller's
DMA0-4 Interrupt Control Register
• Interrupt priority level
• Transfers disabled
Set DMA0 Channel Control Register 0
Set DMA0-4 Interrupt Request Status Registers 0 and 1
Set DMA0-4 Interrupt Request Mask Register
• Interrupt request status
bits cleared
• Interrupt request enabled
• Source address of transfer
• Destination address of transfer
Setting
DMAC-related
registers
Set DMA0 Source Address Register
Set DMA0 Destination Address Register
Set DMA0 Count Register
• Number of times DMA transfer
is performed
Set DMA0 Channel Control Registers 0 and 1
• Transfer mode, request source,
transfer size, address direction
and transfer enable
DMA transfer starts as requested by
internal peripheral I/O
Starting DMA transfer
Transfer count register underflows
Interrupt request generated
DMA transfer
completed
DMA operation
completed
Figure 9.3.1 Example of a DMA Transfer Processing Procedure
32180 Group User’s Manual (Rev.1.0)
9-33
RENESAS [ RENESAS TECHNOLOGY CORP ]
