DMAC
9.3 Functional Description of the DMAC
9
Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1
REQSL1
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
0
1
Software start
When any data is written to the DMA1 Software Request Generation Register
When MJT output event bus 0 signal is generated
MJT (output event bus 0)
1
1
0
1
MJT (TIN13 input signal)
When MJT TIN13 input signal is generated
Extended DMA1 transfer request The source selected by the DMA1 Channel Control Register 1 (DM1CNT1)
source selected
REQESEL1 bits (see below)
REQESEL1 DMA Transfer Request Source
DMA Transfer Request Generation Timing
When one DMA0 transfer is completed (cascade mode)
When MJT TIN3 input signal is generated
When MJT TID1 underflow/overflow occurs
0000
0001
0010
One DMA0 transfer completed
MJT (TIN3 input signal)
MJT (TID1_udf/ovf)
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2
REQSL2
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
0
1
Software start
When any data is written to the DMA2 Software Request Generation Register
When MJT output event bus 1 signal is generated
MJT (output event bus 1)
1
1
0
1
MJT (TIN18 input signal)
When MJT TIN18 input signal is generated
Extended DMA2 transfer request The source selected by the DMA2 Channel Control Register 1 (DM2CNT1)
source selected
REQESEL2 bits (see below)
REQESEL2 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
0001
0010
One DMA0 transfer completed
MJT(TID2_udf/ovf)
When one DMA0 transfer is completed (cascade mode)
When MJT TID2 underflow/overflow occurs
CAN(CAN0_S1/S14)
When CAN0 slot 1 transmission failed or slot 14 transmission reception finished
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
32180 Group User’s Manual (Rev.1.0)
9-28
RENESAS [ RENESAS TECHNOLOGY CORP ]
