DMAC
9.3 Functional Description of the DMAC
9
Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3
REQSL3
DMA Transfer Request Source
Software start
DMA Transfer Request Generation Timing
0
0
1
0
1
0
When any data is written to the DMA3 Software Request Generation Register
Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty
Serial I/O1 (reception completed) When serial I/O1 reception is completed
1
1
Extended DMA3 transfer request The source selected by the DMA3 Channel Control Register 1 (DM3CNT1)
source selected
REQESEL3 bits (see below)
REQESEL3 DMA Transfer Request Source
DMA Transfer Request Generation Timing
When MJT TIN0 input signal is generated
When one DMA2 transfer is completed (cascade mode)
When A-D1 conversion is completed
0000
0001
0010
MJT (TIN0 input signal)
One DMA2 transfer completed
A-D1 conversion completed
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4
REQSL4
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
1
0
1
0
Software start
When any data is written to the DMA4 Software Request Generation Register
When one DMA3 transfer is completed (cascade mode)
One DMA3 transfer completed
Serial I/O0 (reception completed) When serial I/O0 reception is completed
1
1
Extended DMA4 transfer request The source selected by the DMA4 Channel Control Register 1 (DM4CNT1)
source selected
REQESEL4 bits (see below)
REQESEL4 DMA Transfer Request Source
DMA Transfer Request Generation Timing
When MJT TIN19 input signal is generated
0000
0001
0010
MJT (TIN19 input signal)
Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty
MJT (TOU1_7irq)
MJT TOU1_7 interrupt source
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
32180 Group User’s Manual (Rev.1.0)
9-29
RENESAS [ RENESAS TECHNOLOGY CORP ]
