Table 1.2 Pin Functions (cont)
Memory Interface
Pin
No. No. Pin Name I/O
Function
Power IO VDD (3.3 V)
Power IO GND (0 V)
Reset
SRAM DRAM SDRAM PCMCIA MPX
197 C15 VDDQ
198 D15 VSSQ
199 B15 MD7/TXD I/O
Mode/SCI
MD7
TXD
TXD
TXD
TXD
TXD
data output
200 A16 SCK2/
05(6(7
I
SCIF clock/
manual reset
05(6(7 SCK2
SCK2
SCK2
SCK2
SCK2
201 C14 VDD
Power Internal VDD
202 D14 VSS
Power Internal GND
(0 V)
203 A15 A18
204 B14 A19
205 C13 VDDQ
206 D13 VSSQ
207 A14 A20
208 B13 A21
209 A13 A22
210 B12 A23
211 C12 VDDQ
212 D12 VSSQ
213 A12 A24
214 B11 A25
O
O
Address
Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
O
Address
Address
Address
Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
Address
Address
215 A11 MD3/&(5$ I/O
Mode/
PCMCIA-CE
MD3
MD4
&(5$
&(5%
216 A10 MD4/&(5% I/O
Mode/
PCMCIA-CE
217 C11 VDDQ
218 D11 VSSQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
219 B10 MD5/5$65 I/O
Mode/5$6
MD5
5$65
(DRAM)
220 A9
221 B9
222 C8
DACK0
DACK1
A0
O
O
O
DMAC0 bus
acknowledge
DMAC1 bus
acknowledge
Address
223 C10 VDDQ
224 D10 VSSQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
Rev. 6.0, 07/02, page 20 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
