Table 1.2 Pin Functions (cont)
Memory Interface
Pin
No. No. Pin Name I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
87
88
89
90
91
92
93
94
95
96
97
98
99
V9
U9
Y9
VDDQ
VSSQ
A9
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
O
Address
W10 A8
Address
Y10 A7
Address
Y11 CKIO
V10 VDDQ
U10 VSSQ
W11 CKIO2
Y12 A6
Clock output
CKIO
CKIO
Power IO VDD (3.3 V)
Power IO GND (0 V)
1
*
CKIO
O
O
O
O
Address
Address
Address
W12 A5
Y13 A4
V11 VDDQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
100 U11 VSSQ
101 W13 A3
O
O
O
Address
Address
102 Y14 A2
103 V12 DRAK1
DMAC1
request
acknowledge
104 U13 DRAK0
O
DMAC0
request
acknowledge
105 V13 VDDQ
106 U12 VSSQ
107 W14 &66
108 Y15 &65
109 V14 VDD
110 U14 VSS
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
Chip select 3
Chip select 2
&66
&65
(&66)
(&65)
&66
&65
&66
&65
Power Internal VDD
Power Internal GND
(0 V)
111 W15 5$6
O
O
5$6
5$6
5$6
&$6
112 Y16 5'/&$66/
Read/&$6/
2(
2(
)5$0(
)5$0(
)5$0(
113 V15 VDDQ
Power IO VDD (3.3 V)
114 U15 VSSQ
Power IO GND (0 V)
Rev. 6.0, 07/02, page 16 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
