Table 1.3 Pin Functions (cont)
Memory Interface
Pin
No.
31
32
33
34
35
36
37
38
39
Pin Name
VDDQ
VSSQ
D15
I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O
I/O
I/O
I/O
I/O
I/O
Data
Data
Data
Data
Data
Data
A15
A0
D0
D14
A14
A1
D1
D13
A13
A2
D2
VDD
Power Internal VDD
(1.8 V)
40
VSS
Power Internal GND
(0 V)
41
42
43
44
45
46
47
48
49
50
51
D12
D3
I/O
I/O
Data
Data
A12
A3
VDDQ
VSSQ
D11
D4
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O
I/O
I/O
I/O
I/O
I/O
O
Data
Data
Data
Data
Data
Data
A11
A4
D10
D5
A10
A5
D9
A9
D6
A6
%$&./
Bus
acknowledge/
bus request
%65(4
52
%5(4/
I
Bus request/bus
acknowledge
%6$&.
53
54
55
D8
I/O
I/O
O
Data
Data
A8
D7
A7
CKE
Clock output
enable
CKE
56
57
58
VDDQ
VSSQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
:(8/&$68/
O
D47–D40 select
signal
:(8
&$68
DQM5
DQM5
Rev. 6.0, 07/02, page 24 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
