Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait
states to be inserted for area 5. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Description
First Cycle
Bit 25: A5W2 Bit 24: A5W1 Bit 23: A5W0
Inserted Wait States
5'< Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
1
6
9
12
15 (Initial value)
Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to
be inserted from the second data access onward in a burst transfer with the burst ROM interface
selected.
Description
Burst Cycle (Excluding First Cycle)
Wait States Inserted from
Bit 22: A5B2
Bit 21: A5B1
Bit 20: A5B0
Second Data Access Onward
5'< Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
2
3
1
4
5
6
7 (Initial value)
Rev. 6.0, 07/02, page 345 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
