Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait
states to be inserted for area 4. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Description
Bit 19: A4W2 Bit 18: A4W1 Bit 17: A4W0
Inserted Wait States
5'< Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
1
6
9
12
15 (Initial value)
Bits 16 and 12—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 15 to 13—Area 3 Wait Control (A3W2–A3W0): These bits specify the number of wait
states to be inserted for area 3. External wait input is only enabled when SRAM interface or MPX
interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX
interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6).
•
When SRAM Interface is Set
Description
Inserted Wait States
Bit 15: A3W2 Bit 14: A3W1 Bit 13: A3W0
5'< Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
1
6
9
12
15 (Initial value)
Rev. 6.0, 07/02, page 346 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
