Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and should only
be written with 0.
Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2–
DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when
switching from a DACK device to another space, or from a read access to a write access on the
same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual
address transfer, inter-area idle cycles are inserted.
Bits 4n + 2 to 4n—Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2–AnlW0): These bits
specify the number of idle cycles between bus cycles to be inserted when switching from external
memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the
same space.
DMAIW2/AnIW2
DMAIW1/AnIW1
DMAIW0/AnIW0
Inserted Idle Cycles
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
2
3
1
6
9
12
15
(Initial value)
Rev. 6.0, 07/02, page 341 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
