Bits 31 to 29—Area 6 Wait Control (A6W2—A6W0): These bits specify the number of wait
states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Description
First Cycle
Bit 31: A6W2 Bit 30: A6W1 Bit 29: A6W0
Inserted Wait States
5'< Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
1
6
9
12
15 (Initial value)
Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to
be inserted from the second data access onward in a burst transfer with the burst ROM interface
selected.
Description
Burst Cycle (Excluding First Cycle)
Wait States Inserted
from Second Data
Bit 28: A6B2
Bit 27: A6B1
Bit 26: A6B0
Access Onward
5'< Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
2
3
1
4
5
6
7 (Initial value)
Rev. 6.0, 07/02, page 344 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
