Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait
states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Description
First Cycle
Bit 5: A0W2
Bit 4: A0W1
Bit 3: A0W0
Inserted Wait States
5'< Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
2
3
1
6
9
12
15 (Initial value)
Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the number of wait states to
be inserted afterwards the second data access in a burst transfer with the burst ROM interface
selected.
Description
Burst Cycle (Excluding First Cycle)
Wait States Inserted from
Bit 2: A0B2
Bit 1: A0B1
Bit 0: A0B0
Second Data Access Onward 5'< Pin
0
0
0
1
0
1
0
1
0
1
0
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
1
1
0
1
2
3
1
4
5
6
7 (Initial value)
Rev. 6.0, 07/02, page 349 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
