VRS51L1050
FIGURE 11: TIMER/COUNTER 1 MODE 0: 13-BIT COUNTER
Mode 3
In Mode 3, Timer 1 is blocked as if its control bit (TR1)
was set to 0. In this mode, Timer 0’s registers (TL0 and
TH0) are configured as two separate 8-bit counters.
The TL0 counter uses Timer 0’s control bits (C/T,
GATE, TR0, INT0, TF0) and the TH0 counter is held in
timer mode (counting machine cycles) and gains
control over TR1 and TF1 from Timer 1. At this point,
TH0 controls the Timer 1 interrupt.
÷12
Fosc
TL1 / TL0
0
1
C/T1 / C/T0 =0
C/T1 / CT0 =1
0
4
7
CLK
Mode 0
Mode 1
Control
T1/T0 pin
TR1/TR0
TH1 / TH0
GATE1 /
GATE0
0
7
INT1 /
INT0 pin
FIGURE 13: TIMER/COUNTER 0 MODE 3
TF1 /
TF0
INT
TH0
0
7
CLK
Mode 1
Control
TF1
INTERRUPT
TR1
Mode 1 is almost identical to Mode 0, with the
difference being that in Mode 1, the counter/timer uses
the timer’s entire 16 bits.
Fosc
÷12
TL0
0
1
C/T =0
C/T =1
0
7
CLK
Control
T0PIN
Mode 2
TF0
INTERRUPT
In this mode, the timer register is configured as an 8-bit
auto-re-loadable counter/timer and TLx is used as a
counter. In the event of a counter overflow, the TFx
flag is set to 1 and the value contained in THx, which is
preset by software, is reloaded into the TLx counter.
The value of THx remains unchanged.
TR0
GATE
INT0 PIN
FIGURE 12: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD
Fosc
÷12
C/T1 / C/T0 = 1
C/T1 / C/T0 = 1
TL1 / TL0
0
1
0
7
Control
T1 / T0 Pin
Reload
0
7
TH1 / TH0
TF1 / TF0
TR1 / TR0
GATE1 / GATE0
INT
INT1 / INT0 pin
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