VRS51L1050
When the port is used as an output, the register
contains information on the state of the output pins.
Measuring the state of an output directly on the pin is
inaccurate because the electrical level depends mostly
on the type of charge that is applied to it. The functions
shown below use the value of the register rather than
that of the pin.
VRS51L1050 Timers
The VRS51L1050 includes three 16-bit timers: Timer
0, Timer 1 and Timer 2.
The timers can operate in two modes:
o
o
Event counting mode
Timer mode
TABLE 22: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER
VALUES
When operating in event counting mode, the counter is
incremented each time an external event, such as a
transition in the logical state of the timer input (T0, T1,
T2 input), is detected. When operating in timer mode,
the counter is incremented by the microcontroller’s
system clock (Fosc/12) or by a divided version of it.
Instruction Function
ANL
ORL
XRL
JBC
CPL
INC
Logical AND ex: ANL P0, A
Logical OR ex: ORL P2, #01110000B
Exclusive OR ex: XRL P1, A
Jump if the bit of the port is set to 0
Complement one bit of the port
Increment the port register by 1
Decrement the port register by 1
Decrement by 1 and jump if the result is not
equal to 0
DEC
DJNZ
Timer 0 and Timer 1
Timers 0 and 1 have four modes of operation. These
modes allow the user to change the size of the
counting register or to enable an automatic reload
when encountering a specific count value. Timer 1 can
also be used as a baud rate generator to generate
communication frequencies for the serial interface.
MOV P.,C
CLR P.x
SETB P.x
Copy the held bit C to the port
Set the port bit to 0
Set the port bit to 1
Port Operation Timing
Writing to a Port (Output)
Timer 1 and 0 are configured by the TMOD and TCON
registers.
When an operation results in a modification of the
content in a port register, the new value is placed at
the output of the D flip-flop (see figure) during the last
machine cycle of the executed instruction.
TABLE 23: TIMER MODE CONTROL REGISTER (TMOD) – SFR 89H
7
6
C/T1
5
T1M1
4
T1M0
3
2
C/T0
1
T0M1
0
T0M0
GATE1
GATE0
Reading a Port (Input)
Bit
Mnemonic Description
7
GATE1
C/T1
1: Enables external gate control (pin INT1 for
Counter 1). When INT1 is high, and the TRx
bit is set (see TCON register), a counter is
incremented every falling edge on the T1IN
input pin.
Selects timer or counter operation (Timer 1).
1 = A counter operation is performed
0 = The corresponding register will function
as a timer.
In order to be sampled, the signal duration present on
the I/O inputs must be longer than Fosc/12.
I/O Ports Driving Capability
6
The maximum allowable continuous current that the
device can sink on an I/O port is described in the
following table:
Selects the operating mode of
Timer/Counter 1
5
4
3
T1M1
T1M0
GATE0
If set, enables external gate control (pin INT0
for Counter 0). When INT0 is high, and the
TRx bit is set (see TCON register), a counter
is incremented every falling edge on the T0IN
input pin.
Nominal Port 0 pin sink current
(0.4V out)
Nominal ports 1, 2, 3, 4 pin sink current
(0.4V out)
4 to 8 mA
3 to 6mA
Selects timer or counter operation (Timer 0).
1 = A counter operation is performed
0 = The corresponding register will function
as a timer.
Selects the operating mode of
Timer/Counter 0.
2
C/T0
Maximum sink current on a given I/O pin 10mA
Maximum total sink current for P0 26mA
Maximum total sink current for P1, 2, 3,4 15mA
Maximum total sink current on all I/O 71mA
1
0
T0M1
T0M0
It is not recommended to exceed the above values for
sink current as doing so may cause the low-level
output voltage to exceed the device’s specification and
affect device reliability. VRS51L1050 I/O ports are not
designed to source current.
The table below summarizes the four modes of
operation of timers 0 and 1. The timer operating mode
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