VRS51L1050
TABLE 16: PORT 0 REGISTER (P0) - SFR 80H
Port P0 and P2 as Address and Data Bus
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
The output stage may derive its data from two sources:
o
o
The outputs of register P0 or the bus address
itself multiplexed with the data bus for P0.
The outputs of the P2 register or the high byte
(A8 through A15) of the bus address for the P2
port.
Bit
7
6
5
4
3
2
1
0
Mnemonic Description
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Each bit of the P0 register corresponds to
an I/O line:
0: Output transistor pulls the line to 0V
1: Output transistor is blocked so the pull-
up brings the I/O to 3.3V
FIGURE 9: P2 PORT STRUCTURE
Read Register
Port 2
Vcc
Address
Port P2 is similar to Port 1 and Port 3, the difference
being that P2 is used to drive the A8-A15 lines of the
address bus when the EA line of the VRS51L1050 is
held low at reset time, or when a MOVX instruction is
executed.
Pull-up
Network
Q
Q
Internal Bus
IC Pin
D Flip-Flop
Write to
Register
X1
Control
Like the P0, P1 and P3 registers, the P2 register is bit-
addressable.
Read Pin
TABLE 17: PORT 2 REGISTER (P2) - SFR A0H
When the ports are used as an address or data bus,
special function registers P0 and P2 are disconnected
from the output stage, the 8 bits of the P0 register are
forced to 1 and the contents of the P2 register remain
constant.
7
6
5
4
3
P2.3
2
P2.2
1
P2.1
0
P2.0
P2.7
P2.6
P2.5
P2.4
Bit
7
6
5
4
3
2
1
0
Mnemonic Description
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
Each bit of the P2 register corresponds to
an I/O line:
Port 1
0: Output transistor pulls the line to 0V
1: Output transistor is blocked so the pull-
up brings the I/O to 3.3V
The P1 register controls the direction of the Port 1 I/O
pins. Writing a 1 into the P1.x bit (see the following
table) of the P1 register configures the bit as an output,
presenting a logic 1 to the corresponding I/O pin, or
enables use of the I/O pin as an input. Writing a 0
activates the output “pull-down” transistor which will
force the corresponding I/O line to a logic low.
TABLE 18: PORT 1 REGISTER (P1) - SFR 90H
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Bit
7
6
5
4
3
2
1
0
Mnemonic Description
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Each bit of the P1 register corresponds to
an I/O line:
0: Output transistor pulls the line to 0V
1: Output transistor is blocked so the pull-
up brings the I/O to 3.3V
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