VRS51L1050
UART Serial Port
TABLE 29: SERIAL PORT CONTROL REGISTER (SCON) – SFR 98H
7
SM0
6
SM1
5
SM2
4
REN
3
TB8
2
RB8
1
TI
0
RI
The VRS51L1050’s serial port operates in full duplex
mode (transmits and receives data simultaneously).
This occurs at the same speed if one timer is assigned
as the clock source for both transmission and
reception, and at different speeds if transmission and
reception are each controlled by their own timer.
Bit
Mnemonic Description
7
6
5
SM0
SM1
SM2
Bit to select mode of operation (see
following table)
Bit to select mode of operation (see
following table)
Multiprocessor communication is possible
in modes 2 and 3.
In modes 2 or 3, if SM2 is set to 1, RI will
not be activated if the received 9th data bit
(RB8) is 0.
In Mode 1, if SM2 = 1, RI will not be
activated if a valid stop bit was not
received.
Serial Reception Enable Bit
This bit must be set by software and
cleared by software.
1: Serial Reception Enabled
0: Serial Reception Disabled
9th data bit transmitted in modes 2 and 3.
This bit must be set and cleared by
software.
9th data bit received in modes 2 and 3.
In Mode 1, if SM2 = 0, RB8 is the stop bit
that was received.
The VRS51L1050 serial port includes a double buffer
for the receiver, which allows reception of a byte even
if the processor has not retrieved the previously
received byte from the receive register. However, if the
first byte still has not been read by the time reception
of the second byte is complete, the byte present in the
receive buffer will be lost.
4
REN
The SBUF register provides access to the transmit and
receive registers of the serial port. Reading from the
SBUF register will access the receive register, while a
write to the SBUF loads the transmit register.
3
2
TB8
RB8
Serial Port Control Register
The SCON (serial port control) register contains control
and status information, and includes the 9th data bit for
transmit/receive (TB8/RB8 if required), mode selection
bits and serial port interrupt bits (TI and RI).
In Mode 0, this bit is not used.
This bit must be cleared by software.
Transmission Interrupt Flag.
1
0
TI
Automatically set to 1 when:
• The 8th bit has been sent in Mode 0.
• The stop bit has been sent in the other
modes.
This bit must be cleared by software.
Reception Interrupt Flag
RI
Automatically set to 1 when:
• The 8th bit has been received in Mode 0.
• The stop bit has been sent in the other
modes (see SM2 exception).
This bit must be cleared by software.
TABLE 30: SERIAL PORT MODES OF OPERATION
SM0
0
0
SM1
0
1
Mode
Description
Baud Rate
Fosc/12
Variable
Fosc/64 or
Fosc/32
0
1
2
Shift Register
8-bit UART
9-bit UART
1
0
1
1
3
9-bit UART
Variable
UART Operating Modes
The VRS51L1050’s serial port operates in four
different modes. In all four modes, a transmission is
initiated by an instruction that uses the SBUF register
as a destination register. In Mode 0, reception is
initiated by setting RI to 0 and REN to 1. An incoming
start bit initiates reception in the other modes, provided
that REN is set to 1. The following sections describe
these four modes.
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