VRS51L1050
TABLE 25: TIMER 0 AND 1 CONTROL REGISTER (TCON) –SFR 88H
is selected by bits T1M1/T1M0 and T0M1/T0M0 of the
TMOD register.
7
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
TF1
TABLE 24: TIMER/COUNTER MODE DESCRIPTION SUMMARY
Bit
7
Mnemonic Description
M1 M0 Mode Function
TF1
Timer 1 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
0
0
1
0
1
0
Mode 0
Mode 1
Mode 2
13-bit Counter
16-bit Counter
8-bit auto-reload Counter/Timer. The reload
value is kept in TH0 or TH1, while TL0 or TL1
is incremented every machine cycle. When TLx
overflows, the value of THx is copied to TLx.
If Timer 1 M1 and M0 bits are set to 1, Timer 1
stops.
6
TR1
TF0
Timer 1 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Timer 0 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware when processor vectors to
interrupt routine.
1
1
Mode 3
5
Timer 0, Timer 1 Counter / Timer Functions
Timer 0 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Interrupt Edge Flag. Set by hardware when
external interrupt edge is detected. Cleared
when interrupt processed.
Interrupt 1 Type Control Bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
Interrupt 0 Edge Flag. Set by hardware
when external interrupt edge is detected.
Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
4
3
TR0
IE1
Timing Function
When Timer 1 or Timer 0 is configured to operate as a
timer, its value is automatically incremented at every
machine cycle. Once the timer value rolls over, a flag
is set and the counter is set to zero. The overflow flags
(TF0 and TF1) are located in the TCON register.
2
1
0
IT1
IE0
IT0
The TR0 and TR1 bits of the TCON register gate the
corresponding timer operation. In order for the timer to
run, the corresponding TRx bit must be set to 1. The
IT0 and IT1 bits of the TCON register control the event
that will trigger the external interrupt as follows:
Counting Function
IT0 = 0: INT0, if enabled, occurs if a low level is
present on P3.2
When operating as a counter, the timer’s register is
incremented at every falling edge of the T0 and T1
signals located at the input of the timer.
IT0 = 1: INT0, if enabled, occurs if a high to low
transition is detected on P3.2
When the sampling circuit sees a high immediately
followed by a low in the next machine cycle, the
counter is incremented. Two machine cycles are
required to detect and record an event. To be properly
sampled, the duration of the event presented to the
timer input should be greater than 1/24 of the oscillator
frequency.
IT1 = 0: INT1, if enabled, occurs if a low level is
present on P3.3
IT1 = 1: INT1, if enabled, occurs if a high to low
transition is detected on P3.3
The IE0 and IE1 bits of the TCON register are external
flags that indicate that a transition has been detected
on the INT0 and INT1 interrupt pins, respectively.
Timer 0 / Timer 1 Operating Modes
The user may change the operating mode by setting
the M1 and M0 bits of the TMOD SFR.
If the external interrupt is configured as edge sensitive,
the corresponding IE0 and IE1 flag is automatically
cleared when the corresponding interrupt is serviced.
Mode 0
If the external interrupt is configured as level sensitive,
the corresponding flag must be cleared by the
software.
A schematic representation of this mode of operation is
presented in the following figure. In Mode 0, the timer
operates as 13-bit counter made up of 5 LSBs from the
TLx register and 8 upper bits from the THx register.
When an overflow causes the value of the register to
roll over to 0, the TFx interrupt signal goes to 1. The
count value is validated as soon as TRx goes to 1 and
the gate bit is 0, or when INTx is 1.
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