VRS51L1050
The Timer 2 mode selection bits and their function are
described in the following table.
Timer 2
Timer 2 of the VRS51L1050 is a 16-bit timer/counter
and is similar to timers 0 and 1 in that it operates as
either an event counter or a timer. This is controlled by
the C/T2 bit in the T2CON special function register.
Timer 2 has three operating modes - auto-load, capture
and baud rate generator. These modes are selected
via the T2CON SFR. The following table describes
T2CON special function register bits:
TABLE 27: TIMER 2 MODE SELECTION BITS
CP/RL2
0
RCLK + TCLK
0
TR2 MODE
16-bit Auto-
1
1
Reload Mode
16-bit Capture
Mode
0
1
Baud Rate
Generator Mode
Timer 2 Stops
1
X
X
1
0
TABLE 26: TIMER 2 CONTROL REGISTER (T2CON) –SFR C8H
X
7
TF2
6
EXF2
5
4
3
2
TR2
1
C/T2
0
RCLK
TCLK
EXEN2
CP/RL2
The modes are discussed in the following sections.
Bit
Mnemonic Description
Timer 2 Overflow Flag: Set by an overflow
of Timer 2 and must be cleared by
software. TF2 will not be set when either
RCLK =1 or TCLK =1.
Timer 2 external flag change in state occurs
when either a capture or reload is caused
by a negative transition on T2EX and
EXEN2=1. When Timer 2 is enabled,
EXF=1 will cause the CPU to vector to the
Timer 2 interrupt routine. Note that EXF2
must be cleared by software.
Serial Port Receive Clock Source.
1: Causes Serial Port to use Timer 2
overflow pulses for its receive clock in
modes 1 and 3.
0: Causes Timer 1 overflow to be used for
the serial port receive clock.
7
TF2
Timer 2 Capture Mode
In Capture Mode, the EXEN2 bit of the T2CON register
controls whether an external transition on the T2EX pin
will trigger a capture of the timer value.
6
EXF2
When EXEN2 = 0, Timer 2 acts as a 16-bit timer or
counter, which, upon overflowing, will set the TF2 bit
(Timer 2 overflow bit). This overflow can be used to
generate an interrupt.
5
4
3
RCLK
TCLK
FIGURE 14: TIMER 2 IN CAPTURE MODE
FOSC
÷12
Serial Port Transmit Clock.
0
1
TIMER
TL2
TH2
0
0
7
7
0
0
7
7
1: Causes serial port to use Timer 2
overflow pulses for its transmit clock in
modes 1 and 3.
0: Causes Timer 1 overflow to be used for
the serial port transmit clock.
Timer 2 External Mode Enable.
1: Allows a capture or reload to occur as a
result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial
port.
C/T2
COUNTER
T2 pin
RCAP2L
RCAP2H
TR2
EXEN2
TF2
T2EX pin
EXF2
EXEN2
0: Causes Timer 2 to ignore events at
T2EX.
Timer 2
Interrupt
Start/Stop Control for Timer 2.
1: Start Timer 2
0: Stop Timer 2
Timer or Counter Select (Timer 2)
1: External event counter falling edge
triggered.
0: Internal Timer (OSC/12)
Capture/Reload Select.
1: Capture of Timer 2 value into RCAP2H.
RCAP2L is performed if EXEN2=1 and a
negative transitions occurs on the T2EX
pin. The capture mode requires RCLK and
TCLK to be 0.
2
1
TR2
When EXEN2 = 1, the above still applies. However, it
is also possible to allow a 1 to 0 transition at the T2EX
input to cause the current value stored in the Timer 2
registers (TL2 and TH2) to be captured in the RCAP2L
and RCAP2H registers. Furthermore, the transition at
T2EX causes bit EXF2 in T2CON to be set, and EXF2,
like TF2, can generate an interrupt. Note that both
EXF2 and TF2 share the same interrupt vector.
C/T2
0
CP/RL2
Timer 2 Auto-Reload Mode
0: Auto-reloads will occur either with Timer
2 overflows or negative transitions at T2EX
when EXEN2=1. When either RCK =1 or
TCLK =1, this bit is ignored and the timer is
forced to auto-reload on Timer 2 overflow.
Additionally in this mode, there are two options
controlled by the EXEN2 bit in the T2CON register.
If EXEN2 = 0, when Timer 2 rolls over, it not only sets
TF2, but also causes the Timer 2 registers to be
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