VRS51L1050
zeros. Once these conditions are met, the deactivation
of SEND and the setting of T1 occur at T1 of the 10th
machine cycle after the “write to SBUF” pulse.
UART Operation in Mode 0
In this mode, serial data enters and exits through the
RXD pin. TXD is used to output the shift clock. The
signal is composed of eight data bits starting with the
LSB. The baud rate in this mode is 1/12 the oscillator
frequency.
UART Reception in Mode 0
When REN and R1 are set to 1 and 0, respectively,
reception is initiated. Bits 11111110 are written to the
receive shift register at the end of the next machine
cycle by the RX control unit. In the following phase, the
RX control unit will activate RECEIVE.
FIGURE 17: SERIAL PORT MODE 0 BLOCK DIAGRAM
Internal Bus
1
Write to
SBUF
The contents of the receive shift register are shifted
one position to the left at the end of every machine
cycle during which RECEIVE is active. The value that
comes in from the right is the value that was sampled
at the P3.0 pin.
Q
S
D
SBUF
RXD P3.0
Shift
CLK
ZERO DETECTOR
Shift
Clock
TXD P3.1
Shift
Start
TX Control Unit
TX Clock
Send
Fosc/12
TI
1’s are shifted out to the left as data bits are shifted in
from the right. The RX control block is flagged to do
one last shift and load SBUF when the 0 that was
initially loaded into the rightmost position arrives at the
leftmost position in the shift register.
Serial Port
Interrupt
RI
RX Clock
Receive
RX Control Unit
RI
REN
Start Shift
1
1
1
1
1
1
1
0
RXD P3.0
Input Function
RXD P3.0
Shift Register
READ SBUF
SBUF
Internal Bus
UART Transmission in Mode 0
Any instruction that uses SBUF as a destination
register may initiate a transmission. The “write to
SBUF” signal also loads a 1 into the 9th position of the
transmit shift register and informs the TX control block
to begin a transmission. The internal timing is such that
one full machine cycle will elapse between a write to
SBUF instruction and the activation of SEND.
The SEND signal enables the output of the shift
register to the alternate output function line of P3.0 and
enables SHIFT CLOCK to the alternate output function
line of P3.1.
At every machine cycle in which SEND is active, the
contents of the transmit shift register is shifted to the
right by one position.
Zeros come in from the left as data bits shift out to the
right. The TX control block sends its final shift and
deactivates SEND while setting T1 after one condition
is fulfilled. When the MSB of the data byte is at the
output position of the shift register; the 1 that was
initially loaded into the 9th position is just to the left of
the MSB; and all positions to the left of that contain
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