VRS51L1050
reloaded with the 16-bit value in the RCAP2L and
RCAP2H registers previously initialized. In this mode,
Timer 2 can be used as a baud rate generator source
for the serial port.
Special Features of Timer 2
Timer 2 on the VRS51L1050 incorporates unique
features uncommon to standard 8051s. These include:
•
•
Timer 2 Output
Optional Down Counting
If EXEN2=1, Timer 2 still performs the above
operation, however, additionally, a 1 to 0 transition at
the external T2EX input will trigger an anticipated
reload of Timer 2 with the value stored in RCAP2L,
RCAP2H and set EXF2.
These special features can be activated through the
T2MOD register located at SFR address C9h.
TABLE 28: TIMER 2 SPECIAL MODE REGISTER (T2MOD) –SFR C9H
FIGURE 15: TIMER 2 IN AUTO-RELOAD MODE
7
6
5
4
3
2
1
0
T2OE
CDOWN
FOSC
÷12
Bit
7:2
1
Mnemonic Description
-
0
1
TIMER
TL2
TH2
0
0
7
7
0
0
7
7
C/T2
Timer 2 Output Enable
0: Timer 2 Output Disabled
1: Timer 2 output Disabled
T2OE
COUNTER
0
1
T2 pin
RCAP2L
RCAP2H
TR2
Timer 2 Down Count Enable
0: Timer 2 Counts Up
T2OE
0
CDOWN
TF2
1: Timer 2 Counts Down
T2EX pin
EXF2
EXEN2
The T2OE bit, when set to 1, will configure the T2
(P1.0) Pin as a Timer 2 output. If the T2OE bit is
cleared, the T2 Pin acts as a Timer 2 event counter
input if the C/T2 bit of T2CON is set to 1.
Timer 2
Interrupt
Timer 2 Baud Rate Generator Mode
Timer 2 can be used for UART baud rate generation.
This mode is activated when RCLK is set to 1 and/or
TCLK is set to 1. This mode is described further in the
serial port section.
When T2OE is set to 1 the T2 Pin will toggle each time
Timer 2 overflows.
The Timer 2 output function is incompatible with the
Timer 2 event counter mode. When Timer 2 is
configured as an event counter (C/T2 = 0), the T2OE
must be cleared.
FIGURE 16: TIMER 2 IN AUTOMATIC BAUD GENERATOR MODE
FOSC
÷2
The CDOWN bit, when set to 1, will cause Timer 2 to
count down from FFFF to 0000h. However, if Timer 2 is
configured in auto-reload mode, it will count from FFFF
down to the reload value stored in the RCAP2H,
RCAP2L registers.
0
1
TIMER
TL2
TH2
0
0
7
0
0
7
7
C/T2
COUNTER
0
1
7
RCAP2L
RCAP2H
TR2
T2 pin
1
0
TX Clock
RX Clock
When the CDOWN bit is cleared, Timer 2 counts from
the reload value up to FFFFh.
÷16
÷16
TCLK
1
0
T2OE
0
1
Timer 1 Overflow
÷2
RCLK
SMOD
Timer 2
Interrupt
Request
T2EX pin
EXF2
EXEN2
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