VRS51L1050
The following table describes the auxiliary functions of
the Port 3 I/O pins.
Auxiliary Port 1 Functions
The Port 1 I/O pins are shared with the I²C-compatible
interface, the PWM outputs, Timer 2 EXT and T2
inputs, as shown below:
TABLE 20: P3 AUXILIARY FUNCTION TABLE
Pin
Mnemonic
Function
P3.0
RXD
Serial
Port:
Receive
data
in
asynchronous mode. Input and output
data in synchronous mode
Pin
P1.0 T2
P1.1 T2EX
Mnemonic
Function
Timer 2 counter input
Timer2 auxiliary input
P3.1
TXD
Serial
Port:
Transmit
data
in
asynchronous mode. Output clock value
in synchronous mode
External Interrupt 0
Timer 0 Control Input
External Interrupt 1
Timer 1 Control Input
Timer 0 Counter Input
Timer 1 Counter Input
Write signal for external memory
P1.2
PWM0 output
PWM1 output
PWM0
P1.3 PWM1
P1.4
P1.5
P3.2
P3.3
INT0
INT1
P1.6
I²C SCL
I²C SDA
SCL
P3.4
P3.5
P3.6
T0
T1
P1.7
SDA
WR
RD
Port 3
P3.7
Read signal for external memory
The structure of Port 3 is similar to that of Port 1.
Port 4
TABLE 19: PORT 3 REGISTER (P3) - SFR B0H
7
P3.7
6
P3.6
5
P3.5
4
P3.4
3
P3.3
2
P3.2
1
P3.1
0
P3.0
Port 4 has four related I/O pins and its port address is
located at 0D8H.
TABLE 21: PORT 4 (P4) - SFR D8H
Bit
7
6
5
4
3
2
1
0
Mnemonic Description
7
6
5
4
3
P4.3
2
P4.2
1
P4.1
0
P4.0
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
Each bit of the P3 register corresponds to
an I/O line:
Unused
Bit
Mnemonic Description
0: Output transistor pulls the line to 0V
1: Output transistor is blocked so the pull-
up brings the I/O to 3.3V
7
6
5
4
3
2
1
0
Unused
Unused
Unused
Unused
P4.3
P4.2
P4.1
P4.0
-
-
-
-
To configure P3 pins as inputs or use
alternate P3 functions, the corresponding
bit must be set to 1.
Used to output the setting to pins P4.3,
P4.2, P4.1, P4.0, respectively
Auxiliary P3 Port Functions
The Port 3 I/O pins are shared with the UART
interface, INT0 and INT1 interrupts, Timer 0 and Timer
1 inputs, and the #WR and #RD lines when external
memory accesses are performed.
Software Port Control
Some instructions allow the user to read the logic state
of the output pin, while others allow the user to read
the contents of the associated port register. These
instructions are called read-modify-write instructions, a
list of which may be found in the below table.
FIGURE 10: P3 PORT STRUCTURE
Auxiliary
Function: Output
Read Register
Upon execution of these instructions, the contents of
the port register (at least 1 bit) are modified. The other
read instructions take the present state of the input into
account. For example, the instruction ANL P3,#01h
obtains the value in the P3 register; performs the
desired logic operation with the constant 01h; and re-
copies the result into the P3 register. When users want
to take the present state of the inputs into account,
they must first read these states and perform an AND
operation between the read value and the constant.
Vcc
IC Pin
X1
Q
Internal Bus
D Flip-Flop
Write to
Register
Q
Read Pin
Auxiliary
Function: Input
MOV A, P3; State of the inputs in the accumulator
ANL A, #01; AND operation between P3 and 01h
______________________________________________________________________________________________
www.ramtron.com page 14 of 49
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
