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PCS5I9658G-32-LR 参数 Datasheet PDF下载

PCS5I9658G-32-LR图片预览
型号: PCS5I9658G-32-LR
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V LVCMOS 1:10 PLL时钟发生器 [3.3V 1:10 LVCMOS PLL Clock Generator]
分类和应用: 时钟发生器
文件页数/大小: 15 页 / 607 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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November 2006  
rev 0.3  
PCS5I9658  
Applications Information  
stable and optimal operation. Two operating frequency  
ranges are supported: 50 to 125MHz and 100 to 250  
MHz. Table 7 illustrates the configurations supported by  
the PCS5I9658. PLL zero-delay is supported if  
BYPASS=1, PLL_EN=1 and the input frequency is within  
the specified PLL reference frequency range.  
Driving Transmission Lines  
The PCS5I9658 supports output clock frequencies from  
50 to 250MHz. Two different feedback divider  
configurations can be used to achieve the desired  
frequency operation range. The feedback divider  
(VCO_SEL) should be used to situate the VCO in the  
frequency lock range between 200 and 500MHz for  
Table 7: PCS5I9658 Configurations (QFB connected to FB_IN)  
PLL_ VCO_  
Frequency  
Output range (fQ0-7)  
0-250MHz  
BYPASS  
Operation  
EN  
X
SEL  
Ratio  
VCO  
0
1
1
1
1
X
0
1
0
1
Test mode: PLL and divider bypass  
Test mode: PLL bypass  
Test mode: PLL bypass  
PLL mode (high frequency range)  
PLL mode (low frequency range)  
fQ0-9 =fREF  
n/a  
0
0
1
1
fQ0-9 =fREF ÷ 2  
fQ0-9 =fREF ÷ 4  
fQ0-9 =fREF  
0-125MHz  
0-62.5MHz  
100 to 250MHz  
50 to 125MHz  
n/a  
n/a  
fVCO =fREF. 2  
fVCO =fREF. 4  
fQ0-9 =fREF  
RF = 5-15  
CF = 22 µF  
Power Supply Filtering  
RF  
VCC  
VCC_PLL  
The PCS5I9658 is a mixed analog/digital product. Its  
analog circuitry is naturally susceptible to random noise,  
especially if this noise is seen on the power supply pins.  
Random noise on the VCCA_PLL power supply impacts the  
device characteristics, for instance I/O jitter. The  
PCS5I9658 provides separate power supplies for the  
CF  
10 nF  
PCS5I9658  
VCC  
output buffers (VCC) and the phase-locked loop (VCCA_PLL  
)
33…100 nF  
of the device. The purpose of this design technique is to  
isolate the high switching noise digital outputs from the  
relatively sensitive internal analog phase-locked loop. In a  
digital system environment where it is more difficult to  
minimize noise on the power supplies a second level of  
isolation may be required. The simple but effective form  
of isolation is a power supply filter on the VCC_PLL pin for  
the PCS5I9658. Figure 3. illustrates a typical power  
supply filter scheme. The PCS5I9658 frequency and  
phase stability is most susceptible to noise with spectral  
content in the 100KHz to 20MHz range. Therefore the  
filter should be designed to target this range. The key  
parameter that needs to be met in the final filter design is  
the DC voltage drop across the series filter resistor RF.  
From the data sheet the ICC_PLL current (the current  
sourced through the VCC_PLL pin) is typically 12mA  
(20 mA maximum), assuming that a minimum of 2.835V  
must be maintained on the VCC_PLL pin.  
Figure 3. VCC_PLL Power Supply Filter  
noise whose spectral content is above 100KHz. In the  
example RC filter shown in Figure 3.“VCC_PLL Power  
Supply Filter”, the filter cut-off frequency is around  
3-5KHz and the noise attenuation at 100KHz is better  
than 42dB.  
As the noise frequency crosses the series resonant point  
of an individual capacitor its overall impedance begins to  
look inductive and thus increases with increasing  
frequency. The parallel capacitor combination shown  
ensures that a low impedance path to ground exists for  
frequencies well above the bandwidth of the PLL.  
Although the PCS5I9658 has several design features to  
minimize the susceptibility to power supply noise  
(isolated power and grounds and fully differential PLL)  
there still may be applications in which overall  
performance is being degraded due to system power  
supply noise. The power supply filter schemes discussed  
The minimum values for RF and the filter capacitor CF are  
defined by the required filter characteristics: the RC filter  
should provide attenuation greater than 40 dB for  
3.3V 1:10 LVCMOS PLL Clock Generator  
7 of 15  
Notice: The information in this document is subject to change without notice.