November 2006
rev 0.3
PCS5I9658
VCC
VCC ÷2
GND
tP
T0
DC= (tP ÷T0 Χ 100%)
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
Figure 12. Output Duty Cycle (DC)
CCLK
FB_IN
TJIT(Ø) =│T0-T1 mean│
The deviation in t0 for a controlled edge with respect
to a t0 mean in a random sample of cycles
Figure 13.I/O Jitter
T0
TJIT(PER) =│TN-1/f0│
TN
TN-1
TJIT(CC) =│TN-TN-1
│
The deviation in cycle time of a signal with respect to the
ideal period over a random sample of cycles
The variation in cycle time of a signal between adjacent
cycles, over a random sample of adjacent cycle pairs
Figure 15. Period Jitter
Figure 14. Cycle-to-cycle Jitter
VCC = 3.3V
2.4
0.55
tR
tF
Figure 16. Output Transition Time Test Reference
3.3V 1:10 LVCMOS PLL Clock Generator
11 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
