November 2006
rev 0.3
Driving Transmission Lines
PCS5I9658
looking into the driver. The parallel combination of the
36ꢀ series resistor plus the output impedance does not
match the parallel combination of the line impedances.
The voltage wave launched down the two lines will equal:
The PCS5I9658 clock driver was designed to drive high
speed signals in
a
terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 20ꢀ the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50ꢀ
resistance to VCC÷2.
VL = VS ( Z0 ÷(RS+R0 +Z0))
Z0 = 50ꢀ|| 50ꢀ
RS = 36 ꢀ|| 36ꢀ
R0 = 14ꢀ
VL = 3.0 ( 25 ÷(18+14+25))
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the PCS59658 clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 6. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme the fanout of the PCS5I9658 clock driver is
effectively doubled due to its capability to drive multiple
lines.
3.0
OutA
OutB
2.5
2.0
1.5
t
D = 3.8956
t
D = 3.9386
In
1.0
0.5
0
PCS5I9658
OUTPUT BUFFER
Z0=50ꢀ
RS=36ꢀ
IN
IN
14ꢀ
OUTA
2
4
6
8
10
12
14
PCS5I9658
Z0=50ꢀ
Z0=50ꢀ
RS=36ꢀ
RS=36ꢀ
OUTPUT BUFFER
OUTB0
OUTB1
Figure 7. Single versus Dual Waveforms
14ꢀ
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 8. “Optimized Dual
Line Termination” should be used. In this case the series
terminating resistors are reduced such that when the
parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
Figure 6. Single versus Dual Transmission Lines
The waveform plots in Figure 7. “Single versus Dual Line
Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both
cases the drive capability of the PCS5I9658 output buffer
is more than sufficient to drive 50ꢀ transmission lines on
the incident edge. Note from the delay measurements in
the simulations a delta of only 43pS exists between the
two differently loaded outputs. This suggests that the dual
line driving need not be used exclusively to maintain the
tight output-to-output skew of the PCS5I9658. The output
waveform in Figure 7. “Single versus Dual Line
Termination Waveforms” shows a step in the waveform,
this step is caused by the impedance mismatch seen
PCS5I9658
Z0=50ꢀ
RS=22ꢀ
OUTPUT BUFFER
IN
14ꢀ
Z0=50ꢀ
RS=22ꢀ
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
25Ω = 25Ω
Figure 8. Optimized Dual Line Termination
3.3V 1:10 LVCMOS PLL Clock Generator
9 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
