November 2006
PCS5I9658
rev 0.3
Table 1: Pin Configuration
Pin #
Pin Name
I/O
Input
Type
Function
6
7
PCLK,
PCLK
LVPECL LVPECL reference clock signal
2
32
FB_IN
VCO_SEL
Input
Input
LVCMOS PLL feedback signal input, connect to QFB
LVCMOS Operating frequency range select
3
4
5
Input
Input
Input
LVCMOS PLL and output divider bypass select
LVCMOS PLL enable/disable
BYPASS
PLL_EN
LVCMOS Output enable/disable (high-impedance tristate) and device reset
MR/OE
Q0-9
28,26,24,
22,20,18,
16,14,12,
10
Output
LVCMOS Clock outputs
30
QFB
GND
Output
Supply
LVCMOS Clock output for PLL feedback, connect to FB_IN
8,9,13,17
Ground
Negative power supply (GND)
21,25,29
PLL positive power supply (analog power supply). It is recommended
1
VCC_PLL
VCC
Supply
Supply
VCC
to use an external RC filter for the analog power supply pin VCC_PLL
Please see applications section for details.
.
11,15,19,
23,27,31
Positive power supply for I/O and core. All VCC pins must be connected
VCC
to the positive power supply for correct operation
Table 2: Function Table
Control Default
0
1
Test mode with PLL bypassed. The reference
clock (PCLK) is substituted for the internal VCO
output. PCS59658 is fully static and no minimum Selects the VCO output1
frequency limit applies. All PLL related AC
PLL_EN
1
characteristics are not applicable.
Test mode with PLL and output dividers
bypassed. The reference clock (PCLK) is directly
1
1
routed to the outputs. PCS59658 is fully static
and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Selects the output dividers.
BYPASS
VCO ÷ 1 (High frequency range).
fREF = fQ0-9 =2. fVCO
VCO ÷ 2 (Low frequency range).
VCO_SEL
f
REF =fQ0-9 =4.fVCO
Outputs disabled (high-impedance state) and
reset of the device. During reset the PLL
feedback loop is open. The VCO is tied to its
lowest frequency. The length of the reset
pulse should be greater than one reference
clock cycle (PCLK).
MR/OE
0
Outputs enabled (active)
Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1.
3.3V 1:10 LVCMOS PLL Clock Generator
3 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
