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PCS5I9658G-32-LR 参数 Datasheet PDF下载

PCS5I9658G-32-LR图片预览
型号: PCS5I9658G-32-LR
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V LVCMOS 1:10 PLL时钟发生器 [3.3V 1:10 LVCMOS PLL Clock Generator]
分类和应用: 时钟发生器
文件页数/大小: 15 页 / 607 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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November 2006  
PCS5I9658  
rev 0.3  
in this section should be adequate to eliminate power  
supply noise related problems in most designs.  
Figure 4. PCS5I9658 max device-to-device skew  
Due to the statistical nature of I/O jitter a RMS value (1σ)  
is specified. I/O jitter numbers for other confidence factors  
(CF) can be derived from Table 8.  
Using the PCS5I9658 in zero-delay applications  
Nested clock trees are typical applications for the  
PCS5I9658. Designs using the PCS5I9658, as LVCMOS  
PLL fanout buffer with zero insertion delay will show  
significantly lower clock skew than clock distributions  
developed from CMOS fanout buffers. The external  
feedback option of the PCS59658 clock driver allows for  
its use as a zero delay buffer. The PLL aligns the  
feedback clock output edge with the clock input reference  
edge resulting a near zero delay through the device (the  
propagation delay through the device is virtually  
eliminated). The maximum insertion delay of the device in  
zero-delay applications is measured between the  
reference clock input and any output. This effective delay  
consists of the static phase offset, I/O jitter  
(phase or long-term jitter), feedback path delay and the  
output-to-output skew error relative to the feedback  
output.  
Table 8: Confidence Factor CF  
Probability of clock edge within the  
CF  
distribution  
± 1σ  
± 2σ  
± 3σ  
± 4σ  
± 5σ  
± 6σ  
0.68268948  
0.95449988  
0.99730007  
0.99993663  
0.99999943  
0.99999999  
The feedback trace delay is determined by the board  
layout and can be used to fine-tune the effective delay  
through each device. In the following example calculation  
a I/O jitter confidence factor of 99.7% (±3σ) is assumed,  
resulting in a worst case timing uncertainty from input to  
any output of -214pS to 224pS relative to PCLK  
Calculation of part-to-part skew  
(fREF  
=
100MHz, FB=÷4, tjit(φ)=8pS RMS at  
The PCS5I9658 zero delay buffer supports applications  
where critical clock signal timing can be maintained  
across several devices. If the reference clock inputs of  
two or more PCS5I9658 are connected together, the  
maximum overall timing uncertainty from the common  
PCLK input to any output is:  
f
VCO = 400MHz):  
tSK(PP) = [–70pS...80pS] + [–120pS...120pS] +  
[(8Ps . –3)...(8pS . 3)] + tPD, LINE(FB)  
tSK(PP) = [–214pS...224pS] + tPD, LINE(FB)  
t
SK(PP) = t(φ) + tSK(O) + tPD, LINE(FB) + tJIT(φ) .CF  
Due to the frequency dependence of the I/O jitter, Figure  
5. can be used for a more precise timing performance  
analysis.  
This maximum timing uncertainty consist of  
components: static phase offset, output skew, feedback  
board trace delay and I/O (phase) jitter:  
4
PCLK
Common  
t
PD,LINE (FB)  
-t(Ø)  
QFB
Device 1  
t
JIT(Ø)  
Any Q
Device 1  
+t
SK(O)  
+t
(Ø  
QFB
Device 2  
tJIT(Ø)  
Figure 5. Maximum I/O Jitter versus frequency  
Any Q
Device 2  
+t
SK(O)  
Max. skew  
t
SK(PP)  
3.3V 1:10 LVCMOS PLL Clock Generator  
8 of 15  
Notice: The information in this document is subject to change without notice.