November 2006
rev 0.3
PCS5I9658
Z0=50Ω
Z0=50Ω
Differential
Pulse Generator
Z=50Ω
RT=50Ω
RT=50Ω
VTT
VTT
Figure 9. PCLK PCS5I958 AC test reference
VCC
VCC ÷2
GND
VCC
VCC ÷2
GND
tSK(O)
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 10. Output–to–Output Skew tSK(O)
PCLK
PCLK
VPP = 0.8V
VCMR
=
VCC – 1.3V
VCC
VCC ÷2
GND
FB_IN
t(PD)
Figure 11. Propagation Delay (t(PD)). Static phase offset
test reference
3.3V 1:10 LVCMOS PLL Clock Generator
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Notice: The information in this document is subject to change without notice.