November 2006
PCS5I9658
rev 0.3
1
Table 6: AC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C)
Symbol
Characteristics
Min
100
50
Typ
Max
250
Unit
Condition
PLL locked
PLL locked
Input reference frequency
PLL mode, external feedback
÷2 feedback2
MHz
MHz
÷4 feedback3
125
fREF
Input reference frequency in PLL bypass mode4
0
250
500
MHz
MHz
fVCO
fMAX
VCO operating frequency range5
200
Output Frequency
÷2 feedback3
÷4 feedback4
100
250
MHz
PLL locked
PLL locked
50
125
MHz
Peak-to-peak input voltage
PCLK
VPP
500
1000
mV
LVPECL
LVPECL
Common Mode Range
PCLK
6
VCMR
1.2
2.0
VCC-0.9
V
tPW,MIN
Input Reference Pulse Width7
nS
Propagation Delay (static phase offset) 8 PCLK to
FB_IN
t(Ø)
-70
+80
pS
pS
PLL locked
fREF=100MHz
-125
+125
any frequency
Propagation Delay PLL and divider bypass,
PCLK to Q0-9
tPD
tsk(O)
DC
1.0
4.0
120
(T÷2)
+400
1.0
nS
pS
Output-to-output Skew9
(T÷2)
-400
0.1
Output duty cycle10
T÷2
pS
tR ,tF
tPLZ, HZ
Output Rise/Fall Time
Output Disable Time
nS
nS
0.55 to 2.4V
7.0
tPZL, LZ
tJIT(CC)
tJIT(PER)
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
6.0
80
80
nS
pS
pS
I/O Phase Jitter
tJIT(Ø)
fVCO=500MHz and ÷ 2 feedback, RMS (1σ)11
fVCO=500MHz and ÷ 4 feedback, RMS (1σ)
5.5
6.5
pS
pS
PLL closed loop bandwidth 12
PLL mode, external feedback
÷2 feedback3
÷4 feedback4
6-20
2 - 8
MHz
BW
MHz
tLOCK
Maximum PLL Lock Time
10
mS
Note:1. AC characteristics apply for parallel output termination of 50Ω to VTT
.
2. ÷2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
3.÷4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
4.In bypass mode, the PCS5I9658 divides the input reference clock.
5.The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
6.VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(Ø).
7.Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF. 100% and DCREF,MAX = 100% - DCREF,MIN.
8.Valid for fREF=50MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(Ø) [pS] = 50 pS ± (1÷(120 . fREF)).
9.See application section for part-to-part skew calculation in PLL zero-delay mode.
10.Output duty cycle is DC = (0.5 ± 400pS. fOUT) V 100%. E.g. the DC range at fOUT=100MHz is 46%<DC<54%. T = output period.
11.See application section for a jitter calculation for other confidence factors than 1 and a characteristic for other VCO frequencies.
12.-3 dB point of PLL transfer characteristics.
3.3V 1:10 LVCMOS PLL Clock Generator
6 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
