November 2006
PCS5I9658
rev 0.3
Block Diagram
Q
Q
Q
Q
Q
VCC
2-25k
0
1
÷1
÷2
0
1
0
1
÷2
PCLK
&
Ref
PLL
200-500MHz
PCLK
VCO
VCC
25k
Q
Q
FB_IN
FB
VCC
3-25k
Q
Q
PLL_EN
VCO_SEL
Q9
QFB
BYPASS
MR/OE
25k
Figure 1. PCS5I9658 Logic Diagram
Pin Configuration
20
17
19 18
24 23 22 21
GND
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
Q6
Q1
VCC
VCC
Q7
PCS5I9658
GND
Q8
Q0
GND
QFB
VCC
Q9
VCC
VCO_SEL
GND
1
2
3
4
5
6
7
8
Figure 2. PCS5I9658 32-Lead Package Pinout (Top View)
3.3V 1:10 LVCMOS PLL Clock Generator
2 of 15
Notice: The information in this document is subject to change without notice.