PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Pin Name
Type
Pin
No.
Function
AJUST_REQ Input
AC12
The SBI ADD bus justification request signal
(AJUST_REQ) is used to speed up or slow
down the output data rate of the FREEDM-
84A672.
Negative timing adjustments are requested by
asserting AJUST_REQ during the V3 or H3
octet, depending on the tributary type. In
response to this the FREEDM-84A672 will
send an extra byte in the V3 or H3 octet of
the next frame along with a valid APL
indicating a negative justification.
Positive timing adjustments are requested by
asserting AJUST_REQ during the octet
following the V3 or H3 octet, depending on
the tributary type. FREEDM-84A672 will
respond to this by not sending an octet during
the octet following the V3 or H3 octet of the
next frame and deasserting APL to indicate a
positive justification.
AJUST_REQ is sampled on the rising edge of
REFCLK.
AACTIVE
Output AF4
The SBI ADD bus active indicator signal
(AACTIVE) is asserted whenever FREEDM-
84A672 is driving the SBI ADD bus signals,
ADATA[7:0], ADP, APL and AV5.
All other Link Layer devices driving the SBI
ADD bus should monitor this signal (to detect
multiple sources accidentaly driving the bus)
and should cease driving the bus whenever a
conflict is detected.
AACTIVE is updated on the rising edge of
REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
15
PMC [ PMC-SIERRA, INC ]
