PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Table 3 – Any-PHY Packet Interface Signals (70)
Pin Name
Type
Pin
No.
Function
TXCLK
Input
H26
The transmit clock signal (TXCLK) provides
timing for the transmit Any-PHY packet
interface. TXCLK is a nominally 50% duty
cycle, 25 to 50 MHz clock.
TXADDR[0]
TXADDR[1]
TXADDR[2]
TXADDR[3]
TXADDR[4]
TXADDR[5]
TXADDR[6]
TXADDR[7]
TXADDR[8]
TXADDR[9]
TXADDR[10]
TXADDR[11]
TXADDR[12]
Input
K23
J24
The transmit address signals (TXADDR[12:0])
provide a channel address for polling a transmit
channel FIFO. The 10 least significant bits
provide the channel number (0 to 671) while the
3 most significant bits select one of seven
possible FREEDM-84A672 devices sharing a
single external controller. (One address is
reserved as a null address.) The Tx APPI of
each FREEDM-84A672 device is identified by
the base address in the TAPI672 Control
register.
H25
G26
H24
G25
F26
H23
F25
E26
G23
F24
E25
The TXADDR[12:0] signals are sampled on the
rising edge of TXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
18
PMC [ PMC-SIERRA, INC ]
