PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Pin Name
Type
Pin
No.
Function
ADATA[0]
ADATA[1]
ADATA[2]
ADATA[3]
ADATA[4]
ADATA[5]
ADATA[6]
ADATA[7]
Tristat AF5
The SBI ADD bus data signals (ADATA[7:0])
contain the time division multiplexed transmit
data from the up to 84 independently timed
links. Data from each link is transported as a
tributary within the SBI TDM bus structure.
Multiple link layer devices can drive the SBI
ADD bus at uniquely assigned tributary
column positions. ADATA[7:0] are tristated
when the FREEDM-84A672 is not outputting
data on a particular tributary column.
e
AD7
Output AE7
AF7
AD9
AF8
AD10
AC11
ADATA[7:0] are updated on the rising edge of
REFCLK.
ADP
Tristat AD5
The SBI ADD bus parity signal (ADP) carries
the even or odd parity for the ADD bus
signals. The parity calculation encompasses
the ADATA[7:0], APL and AV5 signals.
e
Output
Multiple link layer devices can drive this
signal at uniquely assigned tributary column
positions. ADP is tristated when the
FREEDM-84A672 is not outputting data on a
particular tributary column. This parity signal
is intended to detect accidental link layer
source clashes in the column assignment.
ADP is updated on the rising edge of
REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
13
PMC [ PMC-SIERRA, INC ]
