PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Pin Name
Type
Input
Pin
No.
AB1
AA3
AC1
Function
TCLK[0]
TCLK[1]
TCLK[2]
The transmit line clock signals (TCLK[2:0])
contain the transmit clocks for the 3
independently timed links. TCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e. not part of the HDLC packet).
TCLK[2:0] is nominally a 50% duty cycle
clock between 0 and 51.84 MHz.
The TCLK[n] inputs are invalid and should be
tied low when their associated link is not
configured for operation (i.e. SPEn_EN input
is high).
TD[0]
TD[1]
TD[2]
Output AA2
The transmit data signals (TD[2:0]) contain
the transmit data for the 3 independently
timed links. TD[2:0] contain HDLC packet
data. For certain transmission formats,
TD[2:0] may contain place holder bits or time-
slots. TCLK[n] must be externally gapped
during the place holder positions in the TD[n]
stream. The FREEDM-84A672 supports a
maximum data rate of 51.84 Mbit/s on each
link.
Y4
AB2
TD[2:0] are updated on the falling edge of the
corresponding TCLK[2:0] clock.
SPE1_EN
SPE2_EN
SPE3_EN
Input
Y2
The Synchronous Payload Envelope Enable
signals (SPEn_EN) configure the operation of
the clock/data inputs and the SBI Interface.
When SPEn_EN is low, the corresponding
Synchronous Payload Envelope conveyed on
the SBI interface is unused and the
AA1
W4
corresponding independently timed link
(signals RCLK[n-1], RD[n-1], TCLK[n-1] and
TD[n-1]) is enabled. When SPEn_EN is high,
the corresponding Synchronous Payload
Envelope conveyed on the SBI interface is
enabled and the corresponding independently
timed link is disabled.
SPEn_EN are asynchronous inputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
17
PMC [ PMC-SIERRA, INC ]
