PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Pin Name
Type
Pin
No.
Function
ADETECT[0] Input
ADETECT[1]
AD12
The SBI ADD bus conflict detection signals
(ADETECT[1:0]) may be connected to the
AACTIVE outputs of other link layer devices
sharing the SBI ADD bus. FREEDM-84A672
will immediately tristate the SBI ADD bus
signals ADATA[7:0], ADP, APL and AV5 if
either of ADETECT[1] and ADETECT[0] is
asserted.
AF12
ADETECT[1:0] are asynchronous inputs.
Table 2 – Clock/Data Interface Signals (15)
Pin Name
Type
Pin
No.
Function
RCLK[0]
RCLK[1]
RCLK[2]
Input
T1
R2
P3
The receive line clock signals (RCLK[2:0])
contain the recovered line clock for the 3
independently timed links. RCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e. not part of the HDLC packet).
RCLK[2:0] is nominally a 50% duty cycle
clock between 0 and 51.84 MHz.
The RCLK[n] inputs are invalid and should be
tied low when their associated link is not
configured for operation (i.e. SPEn_EN input
is high).
RD[0]
RD[1]
RD[2]
Input
R4
R3
R1
The receive data signals (RD[2:0]) contain the
recovered line data for the 3 independently
timed links. RD[2:0] contain HDLC packet
data. For certain transmission formats,
RD[2:0] may contain place holder bits or time-
slots. RCLK[n] must be externally gapped
during the place holder positions in the RD[n]
stream. The FREEDM-84A672 supports a
maximum data rate of 51.84 Mbit/s on each
link. RD[2:0] are sampled on the rising edge
of the corresponding RCLK[2:0].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
16
PMC [ PMC-SIERRA, INC ]
