S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x006: Master Clock Monitor
Bit
31:9
8
Type
Function
Unused
RSTDLL
DLLRUN
Default
X
0
X
R/W
R
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
HALFSECCLKA
OBCIFCLKA
IBCIFCLKA
OCLKA
ICLKA
XCLKA
X
X
X
X
X
X
X
SYSCLKA
This register provides activity monitoring on S/UNI-ATLAS-3200 clocks. When a monitored
clock signal makes a low to high transition, the corresponding register bit is set high. The bit will
remain high until this register is read, at which point, all the clock activity bits in this register are
cleared. A lack of transitions is indicated by the corresponding register bit reading low. This
register should be read at periodic intervals to detect clock or DLL failures.
SYSCLKA
The System Clock active (SYSCKLA) bit monitors for low to high transitions on the
SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this
register is read.
XCLKA
The Crystal Clock active (XCKLA) bit monitors for low to high transitions on the XCLK
input. XCLKA is set high on a rising edge of XCLK, and is set low when this register is read.
ICLKA
The Input Clock active (ICLKA) bit monitors for low to high transitions on the
RLU_CLK/TPU_CLK/RlP_CLK/TPP_CLK input. ICLKA is set high on a rising edge of
this clock, and is set low when this register is read.
OCLKA
The Output Clock active (OCLKA) bit monitors for low to high transitions on the
RPU_CLK/TLU_CLK/RPP_CLK/TLP_CLK input. OCLKA is set high on a rising edge of
this clock, and is set low when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
167
PMC [ PMC-SIERRA, INC ]
