S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x005: Master Interrupt Enable #2
Bit
31:23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Default
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bypass_SDQ_E
Output_SDQ_E
Tx_Link_E
Rx_PHY_E
Input_SDQ_E
Tx_PHY_E
Rx_Link_E
Reserved
OCLKDLLERRE
ICLKDLLERRE
SYSCLKDLLERRE
Reserved
Reserved
Reserved
DRAM_ERRE
SPRTYE[7]
SPRTYE[6]
SPRTYE[5]
SPRTYE[4]
SPRTYE[3]
SPRTYE[2]
SPRTYE[1]
SPRTYE[0]
0
The above enable bits control the corresponding interrupt status bits in the S/UNI-ATLAS-3200
Master Interrupt Status #2 register. When an enable bit is set to logic 1, the INTB output is
asserted low when the corresponding interrupt status bit is a logic 1.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
166