S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Rx_PHY_I
The Rx PHY Interrupt bit indicates that the Rx PHY block has declared an interrupt, which
may be read (and cleared) in the RxP Interrupt Register. Only interrupts whose enable bits are
logic 1 in the RxP Interrupt Enable register in section 11.9 will cause this bit to become logic
1.
Tx_Link_I
The Tx Link Interrupt bit indicates that the Tx Link block has declared an interrupt, which
may be read (and cleared) in the TxL Interrupt Register. . Only interrupts whose enable bits
are logic 1 in the TxL Interrupt Enable register in Section 11.10 will cause this bit to become
logic 1.
Output_SDQ_I
The Output SDQ Interrupt bit indicates that the Output SDQ block has declared an interrupt,
which may be read (and cleared) in the Output SDQ Interrupt Register. Only interrupts
whose enable bits are logic 1 in the Output SDQ Interrupts register in Section 11.11 will
cause this bit to become logic 1.
Bypass_SDQ_I
The Bypass SDQ Interrupt bit indicates that the Bypass SDQ block has declared an interrupt,
which may be read (and cleared) in the Bypass SDQ Interrupt Register. Only interrupts
whose enable bits are logic 1 in the Bypass SDQ Interrupts register in Section 11.12 will
cause this bit to become logic 1.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
164
PMC [ PMC-SIERRA, INC ]
