S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
IBCIFCLKA
The Input BCIF Clock Active (IBCIFCLKA) bit monitors for low to high transitions on the
BI_CLK input. IBCIFCLKA is set high on a rising edge of this clock, and is set low when
this register is read.
OBCIFCLKA
The Output BCIF Clock Active (OBCIFCLKA) bit monitors for low to high transitions on the
BO_CLK input. OBCIFCLKA is set high on a rising edge of this clock, and is set low when
this register is read.
HALFSECCLKA
The Half Second Clock Active (HALFSECCLKA) bit monitors for low to high transitions on
the HALFSECCLK input. HALFSECCLKA is set high on a rising edge of this clock, and is
set low when this register is read.
RSTDLL:
The Reset Delay Locked Loop register bit (RSTDLL) controls the resetting of the S/UNI-
ATLAS-3200 DLL components. If this bit is logic 1, the SYSCLK, OCLK, and ICLK DLL
components will be reset.
DLLRUN
The Delay Locked Loop run register bit (DLLRUN). When logic 1, this bit indicates that all
DLL components have locked to their input clocks. This bit is only valid when SYSCLK,
ICIF_CLK, and OCIF_CLK are running.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
168
PMC [ PMC-SIERRA, INC ]
