S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x004: Master Interrupt Enable #1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
OBCIFFULLE
OBOVFLE
IBCIFFULLE
IBPRTYE
IBOVFLE
IBSOCE
UPCAE
UPOVRE
INSRDYE
Reserved
SlowBGE
DeadPHYE
CROE
XCROE
CROFULLE
COSE
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XCOSE
COSFULLE
PHYPOLE
POLE
OAM_FAILE
END_RDIE
SEG_RDIE
END_AISE
SEG_AISE
END_CCE
SEG_CCE
SRCH_ERRE
OAM_ERRE
INVAL_PTI_VCI_E
UNPROV_E
8
7
6
5
4
3
2
1
0
The above enable bits control the corresponding interrupt status bits in the S/UNI-ATLAS-3200
Master Interrupt Status #1 register. When an enable bit is set to logic 1, the INTB output is
asserted low when the corresponding interrupt status bit is a logic 1.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
165
PMC [ PMC-SIERRA, INC ]
