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PM7325-TC 参数 Datasheet PDF下载

PM7325-TC图片预览
型号: PM7325-TC
PDF下载: 下载PDF文件 查看货源
内容描述: S / UNI - ATLAS -3200电信标准产品数据表初步 [S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet Preliminary]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信电路异步传输模式
文件页数/大小: 432 页 / 2222 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet  
Preliminary  
CRC10  
The CRC10 bit forces the generation of the Error Detection Code (EDC) for cells written into  
the insert FIFO. If CRC10 is set to logic 1 prior to assembling the cell in the buffer, the last  
10-bits of the cell are overwritten with the CRC-10 value calculated over the information  
field (payload) of the cell. When CRC10 is logic 1, the last 16 bits of the cell are typically  
written to zero, and the CRC-10 replaces the 10 least significant bits.  
PROC_CELL  
The Cell Process Enable (PROC_CELL) bit controls the processing of the current cell written  
into the insert FIFO. If PROC_CELL was set to logic 1 prior to writing the cell in the buffer,  
the current is subject to all cell processing functions, just as if the cell had been inserted  
through the Input Cell Interface. Therefore, the header information and PHYID must  
correspond to a provisioned VC, or the cell will be discarded.  
If PROC_CELL is logic 0, the current cell is passed to the output cell interface without  
modification, with the exception that appended bytes may be added or stripped off to ensure a  
correct cell length for the selected interface. The cell need not belong to a provisioned  
connection. The cell is not processed.  
PHYID[5:0]  
The PHY identification bits determine the PHY association of the current cell being written  
by the microprocessor. The state of the PHY[5:0] when the WRSOC is set selects the PHY  
device for that cell:  
PHY[5:0] = 000000, PHY #1/Single PHY.  
PHY[5:0] = 000001, PHY #2  
PHY[5:0] = 000010, PHY #3  
PHY[5:0] = 101111, PHY #48.  
WRSOC  
The write start of cell (WRSOC) bit must identify the first word of the current cell that the  
microprocessor is writing. If WRSOC is logic 1, the next word written into the  
Microprocessor Cell Data register becomes the first word of the cell. Subsequent writes to  
the Microprocessor Cell Data register fill the remainder of the cell sequentially, to a total of  
16 writes. If WRSOC is set again before a complete cell is written, the existing contents will  
be overwritten without transmission.  
WRSOC is not readable.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-1990553, Issue 4  
171  
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