S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
DRAM_ERRI
The DRAM_ERRI bit indicates that a DRAM read detected a CRC-10 violation. This bit is
cleared when this register is read.
SYSCLKDLLERRI
The SYSCLK DLL Error Interrupt indicates that the DLL on SYSCLK found that it was
outside of its capture range. This bit is cleared when this register is read.
ICLKDLLERRI:
The Input Clock DLL Error Interrupt indicates that the DLL on ICLK found that it was
outside of its capture range. This bit is cleared when this register is read.
OCLKDLLERRI
The Output Clock DLL Error Interrupt indicates that the DLL on OCLK found that it was
outside of its capture range. This bit is cleared when this register is read.
Rx_Link_I
The Rx Link Interrupt bit indicates that the Rx Link block has declared an interrupt, which
may be read (and cleared) in the RxL Interrupt Register. Only interrupts whose enable bits are
logic 1 in the RxL Interrupt Enable register in Section 11.6 will cause this bit to become logic
1.
Tx_PHY_I
The Tx PHY Interrupt bit indicates that the Tx PHY block has declared an interrupt, which
may be read (and cleared) in the TxP Interrupt Register. Only interrupts whose enable bits are
logic 1 in the TxP Interrupt Enable register in Section 11.7 will cause this bit to become logic
1.
Input_SDQ_I
The Input SDQ Interrupt bit indicates that the Input SDQ block has declared an interrupt,
which may be read (and cleared) in the Input SDQ Interrupt Register. Only interrupts whose
enable bits are logic 1 in the Input SDQ Interrupts register in section 11.8 will cause this bit
to become logic 1.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
163
PMC [ PMC-SIERRA, INC ]
