S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x003: Master Interrupt Status #2
Bit
31:23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
Reserved
Bypass_SDQ_I
Output_SDQ_I
Tx_Link_I
Rx_PHY_I
Input_SDQ_I
Tx_PHY_I
Rx_Link_I
Reserved
OCLKDLLERRI
ICLKDLLERRI
SYSCLKDLLERRI
Reserved
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved
Reserved
DRAM_ERRI
SPRTYI[7]
SPRTYI[6]
SPRTYI[5]
SPRTYI[4]
SPRTYI[3]
SPRTYI[2]
SPRTYI[1]
SPRTYI[0]
0
SPRTYI[7:0]
The SPRTYI[7:0] bits indicate a parity error has been detected on the external SRAM
interface SDAT[63:0], data bus. When logic 1, the SPRTYI[7:0] bits indicate the following:
SPRTYI[7]:Parity error over inputs SDAT[63:56]
SPRTYI[6]:Parity error over inputs SDAT[55:48]
SPRTYI[5]:Parity error over inputs SDAT[47:40]
SPRTYI[4]:Parity error over inputs SDAT[39:32]
SPRTYI[3]:Parity error over inputs SDAT[31:24]
SPRTYI[2]:Parity error over inputs SDAT[23:16]
SPRTYI[1]:Parity error over inputs SDAT[15:8]
SPRTYI[0]:Parity error over inputs SDAT[7:0]
All bits are cleared when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
162
PMC [ PMC-SIERRA, INC ]
