S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
IBPRTYI
When logic 1, the IBPRTYI bit indicates a parity error over the IBDAT[15:0] data bus. This
bit is cleared when this register is read.
IBCIFFULLI
When logic 1, the IBCIFFULLI bit indicates that the Input Backward Cell Interface FIFO is
full, and cannot accept any more cells generated by the opposite direction S/UNI-ATLAS-
3200. This results in the opposite direction’s Output BCIF being backed up. If the
IBCIFFULLI interrupt persists, the rate at which cells are allowed from the BCIF may have
to be increased, so that RDI and Backward Reporting PM cells can be generated at the
appropriate intervals. This bit is cleared when this register is read.
OBOVFLI
When logic 1, the OBOVFLI bit indicates that a cell was written to the Output BCIF when it
was already full. This indicates that one or more cells destined to be routed to the OBCIF
(such as Loopback cells) has been dropped. RDI and Backward PM cells will not be dropped
in this fashion, since the information needed to generate them later is stored in the VC and
PM tables.
OBCIFFULLI
When logic 1, the OBCIFFULLI bit indicates that the Output Backward Cell Interface FIFO
is full, and cannot accept any more cells generated by the Cell Processor. This affects how
often RDI and Backward Reporting PM cells can be generated and sent to the backwards
direction S/UNI-ATLAS-3200. If the OBCIFFULLI interrupt persists, the rate at which cells
are allowed into the cell stream from the BCIF in the backwards direction S/UNI-ATLAS-
3200 may have to be increased, so that RDI and Backward Reporting PM cells can be
generated at the appropriate intervals. This bit is cleared when this register is read.
REG3I
The REG3I bit indicates that at least one bit in Register 0x003, S/UNI-ATLAS-3200 Master
Interrupt Status #2 is currently asserted.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
161
PMC [ PMC-SIERRA, INC ]
