S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
DEADPHYI
The Inoperative PHY Interrupt bit (DEADPHYI) indicates that a PHY has had cells ready to
be transmitted, and has not accepted any cells whatsoever, for a programmable period of
time. The inoperative PHY may be identified by reading the Inoperative PHY Indication
registers.
SlowBGI
The Slow Background Process Interrupt (SlowBGI) indicates that, for three consecutive
seconds, the TAT update background process was unable to complete a full set of background
processing. This may indicate that the S/UNI-ATLAS-3200 is overloaded with both cells and
microprocessor accesses to DRAM or SRAM.
UPCAI
The UPCAI bit indicates that a cell has been written into the Microprocessor Cell extract
FIFO, and is ready for extraction by an external processor. When logic 1, the UPCAI bit
indicates that the EXTCA bit in the Microprocessor Cell Interface Control and Status register
has been asserted. The UPCAI bit is cleared when this register is read.
UPOVRI
The UPOVRI bit indicates that a cell was written to the Output Microprocessor Interface, but
the FIFO was full, and so the cell was discarded.
INSRDYI
The INSRDYI bit indicates the Microprocessor Cell Interface insert FIFO is ready for
another cell. This bit is cleared when this register is read.
IBSOCI
The Input BCIF SOC interrupt indicates that either the IBCIF received a SOC when it was
not expecting it, or did not receive a SOC when it was expecting one. This bit is cleared
when this register is read.
IBOVFLI
The IBOVFLI bit is set to logic 1 when a cell has been written into the Input BCIF when the
IBCIF was already full This bit is cleared when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
160
PMC [ PMC-SIERRA, INC ]
