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PM7325-TC 参数 Datasheet PDF下载

PM7325-TC图片预览
型号: PM7325-TC
PDF下载: 下载PDF文件 查看货源
内容描述: S / UNI - ATLAS -3200电信标准产品数据表初步 [S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet Preliminary]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信电路异步传输模式
文件页数/大小: 432 页 / 2222 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet  
Preliminary  
INVAL_PTIVCII  
The INVAL_PTIVCII bit indicates a cell with an invalid PTI or VCI field has been received.  
When logic 1, the INVAL_PTIVCII bit indicates one or more F5 cells have the PTI field with  
PTI=’111’, F4 cells with an invalid VCI field (VCI 7 through 15) or at least one VP Resource  
Management cell has been received with PTI not equal to ‘110’. This bit is cleared when this  
register is read.  
OAM_ERRI  
The OAMERRI bit indicates one or more OAM cell with an incorrect OAM Type, Function  
Type or Error Detection Code field (CRC-10) has been received. When logic 1, the  
OAMERRI bit indicates one or more errored OAM cells have been received. This bit may  
also indicate one or more Resource Management cell with an incorrect CRC-10 has been  
received. This bit is cleared when this register is read.  
SRCH_ERRI  
The search error bit (SRCHERRI) indicates that a VPI/VCI search in the VC Table has failed  
due to an improperly constructed secondary search table (i.e. the secondary search takes more  
than 45 branches) or a parity bit error on the external SRAM (correlate with SPRTY[7:0]).  
This bit is cleared when this register is read.  
SEG_CCI  
The Seg_CCI bit indicates that a Segment Continuity Check alarm bit in the VC Table has  
changed state. When logic 1, the SEG_CCI bit indicates the Segment_CC_Alarm bit in the  
VC Table has changed state for one or more virtual connections. This bit is cleared when this  
register is read.  
END_CCI  
The END_CCI bit indicates that an End-to-End Continuity Check alarm (in the VC Table)  
has changed state. When logic 1, the END_CCI bit indicates the End_to_End_CC_Alarm bit  
in the VC Table has changed state for one or more virtual connection. This bit is cleared  
when this register is read.  
SEG_AISI  
The SEG_AISI bit indicates that a Segment AIS alarm (in the VC Table) has changed state.  
When logic 1, the SEG_AISI bit indicates the Segment AIS Alarm bit in the VC Table has  
changed state for one or more virtual connections. This bit is cleared when this register is  
read.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-1990553, Issue 4  
157  
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