PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
.
Symbol
Parameter
Signal
Min
Max
Unit
RPHY_CLK frequency
RPHY_CLK duty cycle
RPHY_CLK hold time
33
55
MHz
%
Tdc
Thd
Tq
45
1
/RPHY_ADDR, /RPHY_EN
ns
RPHY_CLK-to-output
delay
RPHY_CLAV, RPHY_SOC
2
12
13
ns
Tsu
Tq
RPHY_CLK setup time
/RPHY_ADDR, /RPHY_EN
RPHY_DATA
5
2
ns
ns
RPHY_CLK-to-output
delay
6.4 Receive UTOPIA Timing
6.4.1 RUTOPIA as the ATM Layer Device
The receive ATM UTOPIA timing signals are compatible with the UTOPIA Level 1 byte-by-byte
specification (refer to Appendix B, “References”, on page 203). Table 19 indicates the receive
UTOPIA signal names and their corresponding UTOPIA designations. The device will not assert
/RATM_EN unless it can receive an entire cell without needing to deassert the /RATM_EN sig-
nal. Refer to section 3.5 “Receive UTOPIA Interface Block (RUTOPIA)” on page 44 for addi-
tional information.
If the receive FIFO will become full after the AAL1gator II reads the current cell, and /RATM_
EMPTY is asserted during byte 51 through byte 53 of that cell, the AAL1gator II will toggle its
/RATM_EN until those bytes become available from the external device, or the other cell in the
external receive FIFO is read. Since the read data is pipelined, this action ensures the internal
receive FIFO will not overflow.
Table 19. Receive Signal Names and Corresponding UTOPIA Designations
Signal Name
RATM_DATA
UTOPIA Name
RxData
RxSOC
RxEnb*
RxEmpty*
RxClk
RATM_SOC
/RATM_EN
/RATM_EMPTY
RATM_CLK
ꢀꢉꢉ
PMC [ PMC-SIERRA, INC ]
