PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Figure 69 shows the timing information for all AAL1gator II-initiated RAM write cycles.
Twh
MEM_ADDR(io)
Twc
Twsu
/MEM_CS(o)
Twp
/MEM_WE(o)
Twdsu
Twdh
MEM_DATA(io)
Figure 69. RAM Write Cycle Timing
Symbol
Parameter
Write cycle
Signals
/MEM_CS
Min
Max
Unit
Twc
Twdh
Twdsu
Twh
Tp-2
ns
ns
ns
ns
Write data hold
Write data setup
Write hold
MEM_DATA
MEM_DATA
Tp-Tch-10
Tch - 4.3
/MEM_CS, MEM_ADDR,
/MEM_WE
Tp -Tch -10
Twsu
Twp
Write setup
MEM_ADDR, /MEM_CS
/MEM_WE
1
ns
ns
Write pulse width
Tch-1.3
Tch+0.3
NOTES: • Tch and Tp are the clock high time and clock period as measured at 1.5 V. See Figure 80 on
page 119 and refer to section 8.6 “Board Requirements for the SRAM Interface” on page 174.
•
•
Test conditions are: /MEM_WE(0) and /MEM_WE(1) at 15 pF; and MEM_DATA, SP_
DATA_EN, SP_DATA_CLK, SP_DATA_DIR, and /MEM_CS at 30 pF; MEM_ADDR and
SP_ADDR_EN at 40 pF.
All outputs are measured at 1.5 V, -40 to 85°C, 4.75 - 5.25 V.
ꢀꢉꢃ
PMC [ PMC-SIERRA, INC ]
