PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
shows the data input timing for the RUTOPIA block in MPHY mode. The timing parameters used
in Figure 68 are defined in the table following the figure. Refer to section 3.5 “Receive UTOPIA
Interface Block (RUTOPIA)” starting on page 44 for additional information.
Thd
Tdc
Tsu
TPHY_CLK(i)
/TPHY_ADDR(i)
Tq
TPHY_CLAV(o)
TPHY_DATA(i)
TPHY_SOC(i)
/TPHY_EN(i)
D1
D2
D3
D4
Figure 68. RUTOPIA MPHY Timing
Symbol
Parameter
Signal
Min
Max
Unit
TPHY_CLK frequency
TPHY_CLK duty cycle
TPHY_CLK hold time
33
55
MHz
%
Tdc
Thd
45
1
/TPHY_ADDR, TPHY_DATA,
TPHY_SOC, /TPHY_EN
ns
Tq
TPHY_CLK-to-output
delay
TPHY_CLAV
12
ns
ns
Tsu
TPHY_CLK setup time
/TPHY_ADDR, TPHY_DATA, TPHY_
SOC, /TPHY_EN
5
6.5 RAM and Microprocessor Timing
6.5.1 RAM Timing
The RAM interface is designed to work with 12 ns SRAMs, which have a write data setup time of
7 ns or less, when SYS_CLK is 40 MHz (the maximum frequency). This interface is asynchro-
nous and the timing parameters are given in this section. If the interface is used at a lower fre-
quency, equations have been provided to calculate the RAM interface timing parameters. The
timing is very dependent on the pulse width of SYS_CLK. The /MEM_WE signals are derived
from the high pulse width of the SYS_CLK input. The high pulse width affects the pulse width of
/MEM_WE and the setup and hold time of MEM_DATA to the rising edge of /MEM_WE.
Refer to section 8.6 “Board Requirements for the SRAM Interface” on page 174 for impor-
tant information about interfacing to different speed SRAMS.
ꢀꢉꢂ
PMC [ PMC-SIERRA, INC ]
