PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
6.3 Transmit UTOPIA Timing
6.3.1 TUTOPIA as the ATM Layer Device
The transmit ATM UTOPIA timing signals are compatible with the ATM Forum UTOPIA Level
1 byte-by-byte specification (refer to Appendix B, “References”, on page 203). Table 17 indicates
the transmit UTOPIA signal names and their corresponding UTOPIA designations. The interface
will not assert /TATM_EN at the beginning of a cell unless it has a full cell to send. After the
AAL1gator II detects /TATM_FULL asserted, it deasserts /TATM_EN two TATM_CLK cycles
later. Refer to section 3.4 “Transmit UTOPIA Interface Block (TUTOPIA)” on page 41 for addi-
tional information.
Table 17. Transmit Signal Names and Corresponding UTOPIA Designations
Signal Name
UTOPIA Name
TATM_DATA
TATM_SOC
/TATM_EN
TxDATA
TxSOC
TxEnb*
TxFull*
TxClk
/TATM_FULL
TATM_CLK
Figure 63 illustrates the transmit ATM UTOPIA timing.
Th
Fc
Tdc
Tsu
TATM_CLK(i)
/TATM_FULL(i)
Tq
/TATM_EN(o)
TATM_SOC(o)
TATM_DATA(o)
53
01
02
03
04
05
06
07
Figure 63. Transmit UTOPIA ATM Timing
Symbol
Parameter
Signals
TATM_CLK
Min
Max
Unit
Fc
Tdc
Tsu
Th
Clock frequency
Clock duty cycle
Clock setup
33
55
MHz
%
TATM_CLK
45
5
/TATM_FULL
ns
Clock hold
/TATM_FULL
1
ns
Tq
Clock-to-output delay
Clock-to-output delay
TATM_SOC, /TATM_EN
TATM_DATA
2
12
13
ns
Tq
2
ns
ꢈꢆ
PMC [ PMC-SIERRA, INC ]
