PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
TL_CLK(i)
TL_FSYNC(i)
TL_MSYNC(i)
CHAN 24, FRAME 24
CHAN 1, FRAME 1
TL_SER(o)
TL_SIG(o)
7
8
1
2
3
4
5
6
7
8
F
1
2
3
4
5
6
7
8
C
D
A
B
C
D
A
B
C
D
Figure 60. Receive Side T1 Interface Frame Timing
In E1 mode, data is driven on the lower four bits of each timeslot as shown in Table 16 on
page 94. Signaling data is driven on the TL_SIG pin for all frames of each multiframe. The
AAL1gator II treats all 32 timeslots the same. Although E1 data streams contain 30 timeslots of
channel data and 2 timeslots of control, data and signaling for all 32 timeslots are stored in mem-
ory.
TL_CLK
TL_FSYNC
TL_MSYNC
CHAN 0, FRAME 0
CHAN 1, FRAME 0
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
TL_SER
TL_SIG
C
D
A
B
C
D
A
B
C
D
A
Figure 61. Receive Side E1 Interface Timing
In UDF-HS mode there is no structure and the data is driven using TL_CLK(0) as shown in
Figure 62.
Fc
Tcp
Tcp
TL_CLK(i)
TL_SER(o)
Tq
Figure 62. Receive Side High-Speed Interface Timing
Symbol
Parameter
Clock frequency
Signals
TL_CLK(0)
Min
Max
Unit
Fc
Tcp
Tq
45
55
13
MHz
%
Clock pulse width
TL_CLK(0)
TL_SER(0)
45
2
Clock-to-output delay
ns
ꢈꢅ
PMC [ PMC-SIERRA, INC ]
